Since the invention of the integrated circuit, the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvement in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limit comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the above-discussed limitations. In a typical formation process of 3D IC, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second substrates.
Much higher device density has been achieved using 3D IC technology, and up to six layers of wafers have been bonded. As a result, the total wire length is significantly reduced. The number of vias is also reduced. Accordingly, 3D IC technology has the potential of being the mainstream technology of the next generation.
Conventional methods for forming 3D IC also include die-to-wafer bonding, wherein one or more die is bonded to a wafer. An advantageous feature of the die-to-wafer bonding is that the size of dies may be smaller than the size of chips on the wafer. During a typical die-to-wafer bonding process, spaces will be left between the dies. The spaces are typically filled with a coating, such as spin-on-glass. The wafer and the dies on wafer are then sawed. However, the conventional die-to-wafer bonding processes have drawbacks. The coating process introduces moisture and chemical contamination, which degrades the bonds between the dies and the wafer. A new die-to-wafer bonding process is therefore needed to solve this problem.